Topic 15: GPU and Accelerator Computing

Description

Accelerators of various kinds offer massive performance and power advantages for suitable applications, at every scale from embedded and mobile to supercomputers and datacenters. Examples include graphics processors (GPUs), "manycore" devices, such as Intel's Xeon Phi and other platforms with large numbers of simple cores, as well as more custom devices, customizable FPGA-based systems and streaming dataflow architectures.

The research challenge for this topic is to explore new technologies for realising this potential. We encourage submissions in all areas related to accelerators: architecture, languages, compilers, libraries, runtime, debugging and profiling tools, algorithms. Papers demonstrating deep engagement with applications and algorithms are particularly welcome, especially where this leads to broader insights on the problems of optimization (for performance and power), programmability, performance portability, support for and integration with legacy code.

Focus

• New accelerator architectures
• Language, Compilers, and Runtime environments for accelerator programming
• Programing clusters of accelerators
• Tools for debugging, profiling, and optimizing programs on accelerator
• Hybrid applications using several accelerator and/or CPUs
• Parallel algorithms for accelerators
• Models and benchmarks for accelerators
• Manual optimization and auto-tuning
• Library support for accelerators

Topic Committee

Global Chair
Paul Kelly, Imperial College London, UK

Local Chair
João Lourenço, Nova University of Lisbon, Portugal

Further Members
Alexander Heinecke, Technische Universität München, Germany
Anton Lokhmotov, ARM, UK
Christian Plessl, University of Paderborn, Germany
Didem Unat, Lawrence Berkeley Lab, US
Dora Blanco Heras, University of Santiago de Compostela, Spain
Lee Howes, Qualcomm, USA
Naoya Maruyama, Tokyo Institute of Technology, Japan
Pedro Gonnet, Durham University, UK